The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
DC-DC converters include a power switch, an inductor, and a diode that transfer energy from an input to an output. Constant frequency DC-DC converters usually set an output current limit by clamping a compensation regulation node to a fixed voltage. Due to the presence of a slope compensation circuit, the current limit will depend on the switching duty cycle or Vin variation.
FIG. 1 shows DC-DC converter 10 that includes an error amplifier 20 including a non-inverting input receiving a reference voltage VREF and an inverting input receiving a feedback voltage VFB. The error amplifier 20 outputs a compensation voltage VCOMP to a non-inverting input of an error comparator 24, a resistor RCOMP connected in series to a capacitor CCOMP, and a clamp circuit 30. The clamp circuit 30 includes a transistor T1 that receives a bias voltage Vbias.
An output of the error comparator 24 is input to a reset input of a flip-flop circuit 28. An output of the flip-flop circuit 28 drives a control terminal of a transistor 31. A first terminal of the transistor 31 is connected between an inductor L1 and an anode of a diode D1. An output of the DC-DC converter 10 is taken at the cathode of the diode D1. A resistive divider including first and second resistors R1 and R2 are connected to the cathode of the diode D1. A node between the resistors R1 and R2 provides the voltage feedback VFB to the error amplifier 20.
A second terminal of the transistor 31 is connected to a current sensor 34 that generates a sensed current ISense. A slope compensation circuit 38 generates a slope compensation current ISL. A resistor RSUM is connected to an output of the current sensor 34, the slope compensation circuit 38, and an inverting input of the error comparator 24.
DC/DC converters that work with a constant frequency architecture and current mode use the slope compensation circuit 38 to add the slope current ISL to the sensed current ISense to remove sub-harmonic instability in the inductor current IL1. Usually the current limit is set by clamping the VCOMP signal to a given value. The clamping voltage is set to: VCLAMP=Vbias+Vbe; hence VCOMP will not exceed this value. The relationship between the inductor current IL and the sensed current Isense is Isense*RSUM=IL*RCS; where RcS the transresistance. VCOMP=(Isense+ISL)*RSUM. The maximum sensed current Isense will be Isense—max=(VCLAMP/RSUM)−ISL.
From the above relationships we can calculate the max inductor current: IL—MAX=(1/RCS)*(VCOMP−ISL*RSUM). ISL is a ramp; therefore the value that should be used in this formula is the slope current at the working duty cycle.
This approach generates a current limit that changes with the input voltage and the output voltage and therefore with the duty cycle as well. The current limit depends on the input and output voltage of the DC-DC converter 10. When the slope compensation signal is large, the current limit will vary and will depend on the duty cycle.